1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, including a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit produced by combining a plurality of transistors, and a source potential switching method for the transistors in the semiconductor integrated circuit.
Especially in the case of a semiconductor integrated circuit configured as a MOS transistor such as an N-channel MOS transistor (hereinafter referred to as an N-ch transistor) or a P-channel MOS transistor (hereinafter referred to as a P-ch transistor), a higher integration and a miniaturization of the semiconductor integrated circuit have been advancing rapidly, and the requirement for a lower voltage of the voltage source and a lower power consumption of the semiconductor integrated circuit tends to increase at present. On the other hand, in order to realize a high operating speed of the semiconductor integrated circuit, a lower threshold voltage between the gate and the source of the MOS transistor is required.
2. Description of the Related Art
Assume that in order to realize the higher integration and miniaturization of the semiconductor integrated circuit as described above, the gate oxide film thickness of the MOS transistor is reduced to 1/k (k: positive number that is equal to 1 or more than 1). In the case in which the durability of the insulation of the gate oxide film remains unchanged, an electric field applied between both terminals of the gate oxide film is required to be constant so as to avoid the dielectric breakdown of the gate oxide film. For this to be achieved, the voltage of the power supply is also required to be reduced to 1/k. In order to realize a high operating speed of the semiconductor integrated circuit, on the other hand, the threshold voltage between the gate and the source of the MOS transistor is also desirably reduced to 1/k. A decreased threshold voltage, however, makes it impossible to cut off the current flowing between the source and the drain, thereby increasing the sub-threshold current during the standby period when the semiconductor integrated circuit is in a standby state.
In order to facilitate understanding of the problems encountered by the increased sub-threshold current during the standby period of a semiconductor integrated circuit such as a conventional level shifter circuit requiring a low-voltage, high-speed operation, the relationship between the voltage between the gate and the source and the sub-threshold current of an ordinary MOS transistor and the configuration and the operation of a conventional level shifter circuit will be explained below with reference to FIGS. 1 to 3 that will be hereinafter described in xe2x80x9cBRIEF DESCRIPTION OF THE DRAWINGSxe2x80x9d.
The graph of FIG. 1 shows the relationship between the voltage between the gate and the source and the current flowing between the source and drain of an ordinary MOS transistor.
In FIG. 1, assuming that Vgs is the voltage between the gate and the source and Ids is the current flowing between the source and the drain of the N-channel transistor in the MOS transistor (abbreviated to N-ch transistor in FIG. 1), the relationship between the voltage between the gate and the source Vgs and the logarithmic value (log(Ids)) of the current Ids is illustrated. Assuming that the voltage Vgs for log(Ids)=I0 is the threshold voltage between the gate and the source, for example, the threshold voltage of the first N-ch transistor {circle around (1)} is given as Vth and the threshold voltage of the second N-ch transistor {circle around (2)} is Vthxe2x80x2. Generally, the current Ids in a region in which the voltage Vgs is lower than the threshold voltage, i.e., the current Ids with the N-ch transistor in an off state (deactivated state) is called the sub-threshold current.
On the other hand, assume that the current for the voltage Vgs=0 V in the first N-ch transistor {circle around (1)} is Idso and the current for the voltage Vgs=0 V in the second N-ch transistor {circle around (2)} is Idsoxe2x80x2. As shown in FIG. 1, suppose that the threshold voltage of the second N-ch transistor {circle around (2)} is lower than the threshold voltage of the first N-ch transistor {circle around (1)}, the currents (Idso and Idsoxe2x80x2) for the voltage Vgs of 0 V are larger for the second N-ch transistor {circle around (2)} than for the first N-ch transistor {circle around (1)}. The ordinate of the graph of FIG. 1 is in a logarithmic scale (log scale). Thus, the current for the voltage Vgs of 0 V increases by several orders of magnitude. In the case in which a negative bias voltage (xe2x88x92Vxe2x80x2, for example) is applied as the voltage Vgs, however, the sub-threshold current remarkably decreases. Even though the absolute value of the negative bias voltage xe2x88x92Vxe2x80x2 may be small, the effect of the negative bias voltage is large since the ordinate of this graph is in a logarithmic scale.
The graph of FIG. 1 shows the relationship between the voltage Vgs and the current Ids flowing between the source and the drain of a N-ch transistor. The same can be said of a P-channel transistor (abbreviated to P-ch transistor in FIG. 1) except that the polarities of the voltage Vgs and the current Ids in the P-ch transistor are opposite to those in the N-ch transistor.
Generally, as the threshold voltage between the gate and the source of the MOS transistor is reduced, the sub-threshold current tends to increase. The sub-threshold current increases in proportion to the ratio (W/L) of the gate width to the gate length of the MOS transistor. Further, as a larger storage capacity, a higher integration and a miniaturization of a semiconductor integrated circuit have been advanced, the total gate widths W of a plurality of MOS transistors formed in the whole semiconductor chip constituting the semiconductor integrated circuit tend to increase. Because of the above-mentioned tendencies, the magnitude of the sub-threshold current has become not negligible.
In order to reduce the sub-threshold current during the standby period, the following protective method has been employed in the prior art. For a word decoder with the large total gate widths of the transistors, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 6-203558, a method has been employed for reducing the gate width (W) of the transistor connected to a power supply by inserting a transistor having the small gate width between the power supply and a circuit.
Further, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 5-108194, a method has been employed for reducing the current during the standby period by differentiating the bias of the well or the substrate between the activated period when the semiconductor integrated circuit is activated and the standby period during which the semiconductor integrated period is in a standby state.
Furthermore, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 7-38417, a method has been employed in which a resistor or a switching element is inserted between the MOS transistor constituting an inverter and a power supply thereby to impose a negative bias on the MOS transistor, or in which transistors of different threshold values and power supplies of different potentials are used during the activated period and the standby period.
Now, with regard to a level shifter circuit in which the input signal potential is required to be changed at high speed with a low voltage power supply, an explanation will be given of the relationship between the threshold voltage between the gate and source of the MOS transistor and the sub-threshold current.
FIG. 2 is a circuit diagram showing a configuration of a first example of a conventional level shifter circuit. The level shifter circuit shown in FIG. 2 is disclosed in U.S. Pat. No. 4,486,670.
In the level shifter circuit 100 shown in FIG. 2, in order to produce an output signal OUT by converting the potential of an input signal IN from the potential V1 of a first positive power supply to the potential V2 (V1 less than V2) of a second positive power supply, the gates and the drains of a P-ch transistor 101 and a P-ch transistor 102 are interconnected by cross coupling. Further, the level shifter circuit of FIG. 2 includes a first inverter for inverting the polarity of the input signal IN and a second inverter for inverting the signal output from the first inverter and supplying it to the gate of the P-ch transistor 101. The output signal OUT is produced from the drain of the P-ch transistor 102. The first inverter includes a P-ch transistor 107 and a N-ch transistor 108 connected between the first power supply and the third power supply (ground potential V0). On the other hand, the second inverter includes a P-ch transistor 105 and a N-ch transistor 106 interposed between the first power supply and the third power supply.
Further, in the level shifter circuit of FIG. 2, the N-ch transistors 103, 104 with the gate thereof connected to the first power supply are N-ch transistors which are inserted for protecting a transistor having a relatively low durability against the applied voltage such as the N-ch transistor 108 or the N-ch transistor 106, and are not necessary when a voltage level in the power supply is reduced.
For guaranteeing high-speed and stable operation of the level shifter circuit when the voltage level in the power supply is reduced, however, it is necessary to reduce the threshold voltage as much as possible between the gate and the source of the N-ch transistor 108 and the N-ch transistor 106 in the level shifter circuit. Alternatively, it is necessary to considerably increase the gate width of each of the N-ch transistors 106, 108 as compared with the gate width of each of the P-ch transistor 107 and the P-ch transistor 105.
In the case in which the input signal is at a low voltage level (xe2x80x9cLxe2x80x9d (low) level) during the standby period of the level shifter circuit, the N-ch transistor 108 having a relatively large gate width enters an off state (deactivated state), so that the sub-threshold current with the N-ch transistor 108 in an off state increases relatively. In the case in which the input signal is at high voltage level (xe2x80x9cHxe2x80x9d (high) level) during the standby period of the level shifter circuit, on the other hand, the N-ch transistor 106 with the gate width relatively large is in an off state, in which case the sub-threshold current is relatively large.
FIG. 3 is a circuit diagram showing a configuration of a second example of a conventional level shifter circuit. The level shifter circuit of FIG. 3 is a circuit disclosed in the reference xe2x80x9cVery Large Scale Integrated Memoryxe2x80x9d (authored by Kiyoo Ito, published by Baifuhkan on Feb. 5, 1994 (First Edition), pp. 71, lines 7 to 10).
In the level shifter circuit 120 shown in FIG. 3, in order to produce an output signal OUT by converting the potential of the input signal IN from the potential V1 of a first positive power supply to the potential V2 (V1 less than V2) of a second positive power supply, the gates and the drains of the P-ch transistor 121 and the P-ch transistor 122 are interconnected by cross coupling.
Further, in the level shifter circuit of FIG. 3, the drain of the N-ch transistor 123 is connected to the gate of the P-ch transistor 122, and the source of the N-ch transistor 123 is connected to the third power supply of the ground potential V0. On the other hand, the drain of the N-ch transistor 124 is connected to the gate of the P-ch transistor 121, and the source of the N-ch transistor 124 is connected to the third power supply of the ground potential V0. The input signal IN is input to the gate of the N-ch transistor 123 and also, input to the gate of the N-ch transistor 124 through an inverter including the P-ch transistor 125 and the N-ch transistor 126. Also, the output signal OUT is output from the drain of the P-ch transistor 122.
Further, in the level shifter circuit of FIG. 3, in order to guarantee high-speed, stable operation of the level shifter circuit when the power supply is reduced in voltage, as the potential difference which is to be converted by the level shifter circuit (e.g., a difference value brought about between the potential difference V1xe2x88x92V0 and the potential difference V2xe2x88x92V0) becomes large, the threshold voltage between the gate and the source of each of the N-ch transistor 123 and the N-ch transistor 124 in the level shifter circuit is required to be reduced as much as possible. Alternatively, as described above, the gate width of each of the N-ch transistors 123, 124 is required to be considerably large as compared with the gate width of each of the P-ch transistor 121 and the P-ch transistor 122.
In the case in which the input signal is at xe2x80x9cLxe2x80x9d level during the standby period of the level shifter circuit, the N-ch transistor 123 having the relatively large gate width turns off and, as in the case of FIG. 2, the sub-threshold current in an off state becomes relatively large. In the case in which the input signal is at xe2x80x9cHxe2x80x9d level during the standby period of the level shifter circuit, on the other hand, the N-ch transistor 124 having a relatively large gate width, turns off so that, as in the case of FIG. 2, the sub-threshold current in an off state becomes relatively large.
As described above, in the semiconductor integrated circuit such as the level shifter circuit (or the driver transistor circuit described later) requiring a low-voltage, high-speed operation, the voltage reduction of the power supply and the decrease of the threshold voltage between the gate and source of the MOS transistor tend to proceed in cooperation with each other. Specifically, with the advance of a higher integration, a miniaturization and a voltage reduction of the semiconductor integrated circuit, the threshold voltage between the gate and source of the MOS transistor decreases, thereby causing the problem of an increased sub-threshold current during the standby period. In the conventional level shifter circuit, however, no effective measures have been employed for reducing the sub-threshold current during the standby period. Thus the increase in power consumption due to the extraneous current such as the sub-threshold current must be minimized.
The present invention has been developed in view of the problems described above, and the object of the present invention is to provide a semiconductor integrated circuit, such as a level shifter circuit or a driver transistor circuit requiring a low-voltage, high-speed operation, in which power consumption is reduced by reducing the sub-threshold current as much as possible during the standby period.
In order to achieve the object described above, according to the present invention, there is provided a semiconductor integrated circuit comprising a circuit unit including a plurality of transistors having a predetermined function, wherein the source potential of at least one of the transistors which turns off during the standby period of the circuit unit is changed.
Preferably, in a semiconductor integrated circuit according to the present invention, the source potential of at least one transistor (object transistor) adapted to turn off during the standby period of the circuit unit is changed in such a manner that a predetermined bias voltage is applied between the gate and source of the particular transistor at a timing based on the standby period of the circuit unit.
Preferably, a semiconductor integrated circuit according to the present invention is configured so as to reduce the sub-threshold current flowing between the source and drain of at least one transistor which turns off during the standby period of the circuit unit.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit wherein the circuit unit is a level shifter circuit including a plurality of transistors for changing the potential of the input signal upward or downward.
Preferably, in the semiconductor integrated circuit according to the first aspect of the present invention, the timing of changing the source potential of the transistor which turns off during the standby period of the level shifter circuit is set in accordance with the potential change of the input signal or in accordance with a predetermined program instruction.
Preferably, in the semiconductor integrated circuit according to the first aspect of the present invention, a switching element for changing the source potential of one or a plurality of transistors which turn off during the standby period of the level shifter circuit is assigned to the particular transistor. This switching element changes the source potential of the transistor in such a manner that a predetermined bias voltage is applied between the gate and the source of the same transistor (object transistor) during the standby period of the level shifter circuit.
Preferably, in the semiconductor integrated circuit according to the first aspect of the present invention, the level shifter circuit includes at least a transistor of a first conduction type (such as an N-ch transistor) for changing the potential of the input signal and at least a transistor of a second conduction type (such as a P-ch transistor). A switching element for changing the source potential of one or a plurality of transistors of a first conduction type which turn off during the standby period of the level shifter circuit is assigned to the particular transistor of a first conduction type. This switching element includes a transistor of a second conduction type having a drain connected to the source of the transistor of a first conduction type, and the source of the transistor of a second conduction type is connected to a power supply for applying a predetermined bias voltage between the gate and source of the transistor of a first conduction type thereby to supply a signal to the gate of the transistor of a second conduction type for turning on the transistor of a second conduction type during the standby period of the level shifter circuit. Thus, during the standby period of the level shifter circuit, the source potential of the transistor of a first conduction type is kept at a potential substantially equal to the power supply (e.g., a potential lower (or higher) than the potential of the power supply, by a voltage level corresponding to the threshold voltage between the gate and the source of the transistor).
Preferably, in the semiconductor integrated circuit according to the first embodiment of the present invention, the level shifter circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type for changing the potential of the input signal, and in the case in which the sub-threshold current during an off state of the transistor of a first conduction type is larger than the sub-threshold current during an off state of the transistor of a second conduction type, the source potential of the transistor of a first conduction type which turns off during the standby period of the level shifter circuit is changed at a timing based on the standby period.
Preferably, in the semiconductor integrated circuit according to a modified example of the first embodiment of the present invention, the level shifter circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type for changing the potential of the input signal, and a switching element for changing the source potential of one or a plurality of transistors of a second conduction type adapted to turn off during the standby period of the level shifter circuit is assigned to the particular transistor of a second conduction type. This switching element includes a transistor of a first conduction type having a drain connected to the source of the transistor of a second conduction type, and the source of the transistor of a first conduction type is connected to a power supply for applying a predetermined bias voltage between the gate and source of the transistor of a first conduction type. The gate of the transistor of a first conduction type is supplied with a signal for turning on the transistor of a first conduction type during the standby period of the level shifter circuit, so that the source potential of the transistor of a second conduction type is kept at a potential substantially equal to the potential of the power supply during the standby period of the level shifter circuit.
Preferably, in a semiconductor integrated circuit according to a modified example of the first aspect of the present invention, the level shifter circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type for changing the potential of the input signal, wherein, in the case in which the sub-threshold current with the transistor of a second conduction type in an off state is larger than the sub-threshold current with the transistor of a first conduction type in an off state, the source potential of the transistor of a second conduction type which turns off during the standby period of the level shifter circuit is changed at a timing based on the standby period.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising a level shifter circuit in which the gates and the drains of a first P-ch transistor and a second P-ch transistor for converting the potential of the input signal from the potential of the first power supply to the potential of the second power supply are interconnected by cross coupling, and the gate of a selected one of the first and second P-ch transistors is connected to the drain of the first N-ch transistor. The source of the first N-ch transistor of the level shifter circuit is connected to a first power supply through the drain of a third P-ch transistor on the one hand and to a third power supply lower in potential than the first and second power supplies through the drain of the second N-ch transistor on the other hand.
Preferably, in the semiconductor integrated circuit according to the second aspect of the present invention, the input signal is input to the gate of the first N-ch transistor and also, input to the gates of the third P-ch transistor and the second N-ch transistor at the same time. During the standby period of the level shifter circuit, the potential of the input signal becomes equal to the potential of the third power supply so that the first N-ch transistor turns off. At the same time, the third P-ch transistor turns on while the second N-ch transistor turns off, so that the source potential of the first N-ch transistor is kept substantially at the potential of the first power supply during the standby period of the level shifter circuit.
Preferably, in the semiconductor integrated circuit according to the second aspect of the present invention, the timing of changing the source potential of the first N-ch transistor which turns off during the standby period of the level shifter circuit is set in accordance with the potential change of the input signal of the level shifter or in accordance with a predetermined program instruction.
Preferably, in the semiconductor integrated circuit according to the second aspect of the present invention, a switching element configured of the third P-ch transistor and the second N-ch transistor is assigned to one or a plurality of the first N-ch transistors which turn off during the standby period of the level shifter circuit, and a signal for turning on the third P-ch transistor during the standby period of the level shifter circuit is supplied to the gate of the third P-ch transistor in the switching element. Thus, during the standby period of the level shifter circuit, the source potential of one or a plurality of the first N-ch transistors is kept substantially at the potential of the first power supply, so that the source potential of the first N-ch transistor is changed in such a manner that a negative bias voltage is applied between the gate and source of one or a plurality of the first N-ch transistors.
Preferably, in the semiconductor integrated circuit according to the second aspect of the present invention, in the case in which the sub-threshold current with the first N-ch transistor in an off state is larger than the sub-threshold current with the first P-ch transistor and the second P-ch transistor in an off state in the level shifter circuit, the gate of the third P-ch transistor is supplied with a signal for turning on the third P-ch transistor during the standby period of the level shifter circuit, and the source potential of the first N-ch transistor is kept substantially at the potential of the first power supply during the standby period of the level shifter circuit, so that the source potential of the first N-ch transistor is changed in such a manner as to apply a negative bias voltage between the gate and source of the first N-ch transistor.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit comprising a level shifter circuit in which the gates and drains of the first N-ch transistor and the second N-ch transistor for converting the potential of the input signal from the potential of a fourth power supply to the potential of a fifth power supply are interconnected by cross coupling and the gate of one of the first and second N-ch transistors is connected to the drain of the first P-ch transistor. The source of the first P-ch transistor of the level shifter is connected to the fourth power supply through the drain of the third N-ch transistor on the one hand and to the sixth power supply higher in potential than the fourth and fifth power supplies through the drain of the second P-ch transistor on the other hand.
Preferably, in the semiconductor integrated circuit according to the third aspect of the present invention, the input signal is input to the gate of the first P-ch transistor and also, input to the gate of each of the third N-ch transistor and the second P-ch transistor. During the standby period of the level shifter circuit, the potential of the input signal increases to such a high level as to turn off the first P-ch transistor, while at the same time turning on the third N-ch transistor, so that the second P-ch transistor turns off, and the source potential of the first P-ch transistor is kept at the potential of the fourth power supply during the standby period of the level shifter circuit.
Preferably, in the semiconductor integrated circuit according to the third aspect of the present invention, the timing of changing the source potential of the first P-ch transistor which turns off during the standby period of the level shifter circuit is set in accordance with the potential change of the input signal of the level shifter circuit or in accordance with a predetermined program instruction.
Preferably, in the semiconductor integrated circuit according to the third aspect of the present invention, a switching element configured of the third N-ch transistor and the second P-ch transistor is assigned to one or a plurality of the first P-ch transistors which turn off during the standby period of the level shifter circuit, and the gate of the third N-ch transistor in the switching element is supplied with a signal for turning on the third N-ch transistor during the standby period of the level shifter circuit. During the standby period of the level shifter circuit, the source potential of one or a plurality of the first P-ch transistors is kept substantially at the potential of the fourth power supply, and the source potential of the first P-ch transistor is changed in such a manner that a positive bias voltage is applied between the gate and the source of one or a plurality of the first P-ch transistors.
Preferably, in the semiconductor integrated circuit according to the third aspect of the present invention, in the case in which the sub-threshold current with the first P-ch transistor in an off state is larger than the sub-threshold current with each of the first N-ch transistor and the second N-ch transistor in an off state, the gate of the third N-ch transistor is supplied with a signal for turning on the third N-ch transistor during the standby period of the level shifter circuit. During the standby period of the level shifter circuit, the source potential of the first P-ch transistor is kept substantially at the potential of the fourth power supply, so that the source potential of the first P-ch transistor is changed in such a manner that a positive bias voltage is applied between the gate and the source of the first P-ch transistor.
According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a source potential switching circuit for changing the source potential of at least one of a plurality of the transistors which turns off during the standby period of the circuit unit.
Preferably, in the semiconductor integrated circuit according to the fourth aspect of the present invention, the source potential switching circuit changes the source potential of at least one transistor which turns off during the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and source of the particular transistor at a timing based on the standby period of the circuit unit.
Preferably, the semiconductor integrated circuit according to the fourth aspect of the present invention is so configured as to reduce the sub-threshold current flowing between the source and drain of at least one transistor which turns off during the standby period of the circuit unit.
Preferably, in the semiconductor integrated circuit according to the fourth aspect of the invention, the circuit unit is a level shifter circuit including a plurality of transistors for changing the potential of the input signal upward or downward.
Preferably, in the semiconductor integrated circuit according to the fourth aspect of the invention, the present timing of changing the source potential of the transistor adapted to turn off during the standby period of the level shifter circuit is set in accordance with the potential change of the input signal of the level shifter circuit or in accordance with a predetermined program instruction.
Preferably, in the semiconductor integrated circuit according to the fourth aspect of the present invention, the level shifter circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type for changing the potential of the input signal, and in the case in which the sub-threshold current with the transistor of a second conduction type in off state is larger than the sub-threshold current with the transistor of a first conduction type in an off state, the source potential of the transistor of a second conduction type adapted to turn off during the standby period of the level shifter circuit is changed at a timing based on the standby period.
According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit wherein the circuit unit is at least one of a main driver transistor circuit having a plurality of transistors for driving the internal wiring unit of the semiconductor integrated circuit and a preceding-stage driver transistor circuit located in the stage before the main driver transistor circuit.
Preferably, in the semiconductor integrated circuit according to the fifth aspect of the present invention, the timing of changing the source potential of the transistor adapted to turn off during the standby period of the driver transistor circuit is set in accordance with the potential change of the input signal of the driver transistor circuit or in accordance with a predetermined program instruction.
Preferably, in the semiconductor integrated circuit according to the fifth aspect of the present invention, the source potential switching circuit for changing the source potential of one or a plurality of transistors adapted to turn off during the standby period of the driver transistor circuit is assigned to the particular transistor, and the source potential switching circuit changes the source potential of the object transistor in such a manner that a predetermined bias voltage is applied between the gate and source of the object transistor during the standby period of the driver transistor circuit.
Preferably, in the semiconductor integrated circuit according to the fifth aspect of the present invention, the driver transistor circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type, the source potential switching circuit for changing the source potential of the transistor of a first conduction type is assigned to one of a plurality of transistors of a first conduction type adapted to turn off during the standby period of the driver transistor circuit, the source potential switching circuit includes a transistor of a second conduction type having a drain connected to the source of the transistor of a first conduction type, the source of the transistor of a second conduction type is connected to a power supply for applying a predetermined bias voltage between the gate and source of the transistor of a first conduction type, a signal for turning on the transistor of a second conduction type during the standby period of the driver transistor circuit is applied to the gate of the transistor of a second conduction type, and the source potential of the transistor of a first conduction type is kept substantially at the potential of the power supply during the standby period of the driver transistor circuit.
Preferably, in the semiconductor integrated circuit according to the fifth aspect of the present invention, the driver transistor circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type, the source potential switching circuit for changing the source potential of the transistor of a first conduction type is assigned to one or a plurality of transistors of a first conduction type adapted to turn off during the standby period of the driver transistor circuit, the source potential switching circuit includes a second transistor of a first conduction type having a source connected to the source of the transistor of a first conduction type, the drain of the second transistor of a first conduction type is connected to a power supply for applying a predetermined bias voltage between the gate and source of the transistor of a first conduction type, a signal for turning on the second transistor of a first conduction type during the standby period of the driver transistor circuit is applied to the gate of the first transistor of a first conduction type, and the source potential of the transistor of a first conduction type is kept substantially at the potential of the power supply during the standby period of the driver transistor circuit.
Preferably, in the semiconductor integrated circuit according to the fifth aspect of the present invention, the driver transistor circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type, and in the case in which the sub-threshold current with the transistor of a first conduction type in an off state is larger than the sub-threshold current with the transistor of a second conduction type in an off state, the source potential of the transistor of a first conduction type adapted to turn off during the standby period of the driver transistor circuit is changed at a timing based on the standby period.
Preferably, in the semiconductor integrated circuit according to the fifth aspect of the present invention, the driver transistor circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type, the source potential switching circuit for changing the source potential of the transistor of a second conduction type is assigned to one or a plurality of transistors of a second conduction type adapted to turn off during the standby period of the driver transistor circuit, the source potential switching circuit includes a transistor of a first conduction type having a drain connected to the source of the transistor of a second conduction type, the source of the transistor of a first conduction type is connected to a power supply for applying a predetermined bias voltage between the gate and source of the transistor of a second conduction type, a signal for turning on the transistor of a first conduction type during the standby period of the driver transistor circuit is applied to the gate of the transistor of a first conduction type, and the source potential of the transistor of a second conduction type is kept substantially at the potential of the power supply during the standby period of the driver transistor circuit.
Preferably, in the semiconductor integrated circuit according to the fifth aspect of the present invention, the driver transistor circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type, the source potential switching circuit for changing the source potential of the transistor of a second conduction type is assigned to one or a plurality of transistors of a second conduction type adapted to turn off during the standby period of the driver transistor circuit, the source potential switching circuit includes a second transistor of a second conduction type having a source connected to the source of the first transistor of a second conduction type, the drain of the second transistor of a second conduction type is connected to a power supply for applying a predetermined bias voltage between the gate and source of the first transistor of a second conduction type, a signal for turning on the second transistor of a second conduction type during the standby period of the driver transistor circuit is applied to the gate of the second transistor of a second conduction type, and the source potential of the first transistor of a second conduction type is kept substantially at the potential of the power supply during the standby period of the driver transistor circuit.
Preferably, in the semiconductor integrated circuit according to the fifth aspect of the present invention, the driver transistor circuit includes at least a transistor of a first conduction type and at least a transistor of a second conduction type, and in the case in which the sub-threshold current with the transistor of a second conduction type in an off state is larger than the sub-threshold current with the transistor of a first conduction type in an off state, the source potential of the transistor of a second conduction type adapted to turn off during the standby period of the driver transistor circuit is changed at a timing based on the standby period.
According to still another aspect of the present invention, there is provided a source potential switching method for a transistor in a semiconductor integrated circuit wherein, in the case in which a circuit unit having a predetermined function by a combination of a plurality of transistors is formed in the semiconductor integrated circuit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed in such a manner that a predetermined bias voltage is applied between the gate and source of the particular transistor at a timing based on the standby period of the circuit unit, and the potential difference between the gate and source of the particular transistor reduces the sub-threshold current flowing between the source and drain of the transistor.
The semiconductor integrated circuit according to the present invention is intended for a transistor adapted to turn off during the standby period among those transistors having a comparatively large gate width used in a level shifter circuit or a driver transistor circuit required to operate at low voltage and high speed, wherein the source potential of the transistor is changed during the standby period in such a direction as to reduce the sub-threshold current flowing between the source and drain of the same transistor.
More specifically, in the case in which the transistor adapted to turn off during the standby period is a N-ch transistor, the source potential of the same transistor is changed in such a manner that a negative bias voltage is applied between the gate and source of the N-ch transistor during the standby period thereby to reduce the sub-threshold current considerably during the standby period. In the case in which the transistor adapted to turn off during the standby period is a P-ch transistor, on the other hand, the source potential of the same transistor is changed in such a manner that a positive bias voltage is applied between the gate and source of the P-ch transistor during the standby period thereby to reduce the sub-threshold current considerably during the standby period.
Further, in the case in which the sub-threshold current during an off state of the transistor adapted to turn off during the standby period is smaller than the sub-threshold current of the transistor adapted to turn on during the standby period in the main driver transistor circuit in the driver transistor circuit, the transistor of the driver transistor circuit in the preceding stage is included in the present invention. The reason is that the transistor of the main driver transistor circuit for driving the wiring unit often has the large gate width, and normally, the transistor of the main driver transistor circuit is driven by an inverter train (i.e. the preceding-stage driver transistor circuit) with a gate width increased in a predetermined proportion. As a result, the gate width of the transistor in a stage preceding to a transistor having a large gate width is also comparatively increased. As described before, a transistor having a large sub-threshold current in an off state is liable to have a larger sub-threshold current, and therefore produces a larger effect of reducing the sub-threshold current by the above-mentioned technique of changing the source potential. By specifying the transistor for changing the source potential during the standby period, on the other hand, a still larger effect is obtained with a minimum burden on the source potential switching circuit.
In summary, according to the present invention, the sub-threshold current can be remarkably reduced by changing the source potential of the transistor adapted to turn off during the standby period in a level shifter circuit or a driver transistor circuit requiring low-voltage and high-speed operation. Therefore, it is possible to reduce power consumption during the standby period of a semiconductor integrated circuit in which a higher integration, a miniaturization and a reduced voltage are always promoted.